1. Field of the Invention
The invention relates to a sample-and-hold amplifier, and more particularly, to a sample-and-hold amplifier with a native MOS transistor.
2. Description of the Related Art
With decreased size and power consumption of integrated circuits, operation voltage of the integrated circuit has decreased. When level shifting, that is noise, occurs in a low voltage integrated circuit, the low voltage integrated circuit may output wrong signals. Especially, for a low voltage high resolution pipelined analog-digital converter (ADC) in digital applications, noise usually dominates overall signal-to-noise plus distortion ratio (SNDR) performance. The majority of the noise occurs in a sample-and-hold amplifier, which is usually the first stage of the pipelined ADC. Thus, it is important to reduce the noise of the sample-and-hold amplifier.